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Registration: 29.07.2025

Dhanwanth Rao Varala Balaji

Specialization: Design Verification

Skills

UVM
Verilog
C
C++
Excel

Work experience

Design Verification Engineer 1
01.2025 - 07.2025 |Vaaluka Solutions
UVM
● During this project, I led the complete UVM-based verification of a custom Aligner IP designed for dynamic data alignment and transfer, which featured APB, RX, and TX interfaces. ● I created and executed a comprehensive verification plan with over 50 testcases that was reviewed by industry mentors, and successfully achieved 100% functional and code coverage. ● This involved building a complete testbench which included agents, a register and model-based scoreboard, functional coverage implementation, reset handling, and virtual sequences that aligned with UVM best practices. ● Additionally, I built an automated regression flow using a Makefile with random seeding and debugged complex RTL issues through methodical waveform analysis.

Languages

EnglishProficient