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Registration: 30.07.2025

Faisal Saeed Awan

Specialization: Design Verification Engineer
— Design Verification Engineer with 2.5+ years in UVM-based verification of SoC IPs and high-speed interconnects. — Experienced in scalable testbenches, advanced sequences, coverage-driven verification flows, SystemVerilog, Assertions, AXI/APB, VIP integration, and achieving full coverage. — Strong in debugging, automation, and delivering first-pass silicon success.
Git Verilog Linux Functional testing Shell scripting Bitbucket Debugging
— Design Verification Engineer with 2.5+ years in UVM-based verification of SoC IPs and high-speed interconnects. — Experienced in scalable testbenches, advanced sequences, coverage-driven verification flows, SystemVerilog, Assertions, AXI/APB, VIP integration, and achieving full coverage. — Strong in debugging, automation, and delivering first-pass silicon success.
Git Verilog Linux Functional testing Shell scripting Bitbucket Debugging

Skills

Universal Verification Methodology
System Verilog
SoC verification
Debugging
Shell Scripting
Git
Bitbucket
SystemRDL 2.0
Functional Coverage
QuestaSim
Synopsis VCS
IP Verification
Visualizer

Work experience

Design Engineer
since 10.2022 - Till the present day |CoMira Solutions
D2D Interconnect, SystemRDL, UVM, FIFO RTL, ALU
● Designed & implemented UVM testbench from scratch. ● Developed complex sequences for D2D link training & replay verification. ● Integrated & validated VIP-to-VIP protocol compliance for interconnects. ● Achieved 100% functional & code coverage, enabling first-pass silicon success. ● Created reusable AXI/APB verification environments, reducing dev time 30%. ● Verified FIFO with ALU integration via scoreboards & reference models.

Educational background

Electronics (Masters Degree)
2020 - 2023
Ghulam Ishaq Khan Institute of Engineering Sciences and technology
Industrial Electronics Engineering (Bachelor’s Degree)
2011 - 2015
Institute of Industrial Electronics Engineering (IIEE)

Languages

UrduNativeEnglishIntermediateHindiAdvanced