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Registration: 23.11.2025

Miljana Kotarlic

Specialization: Design Verification Engineer
— Design Verification Engineer focused on IP-level SV/UVM: built testbenches, scoreboards, constrained-random tests, and SystemVerilog Assertions (SVA). — Integrated the DUT with RAL and drove functional/code coverage closure. — Motivated to expand into subsystem and SoC-level verification, passionate about verification, and dedicated to continuous learning and growth. PROJECTS — Asynchronous FIFO – Design & Verification using SystemVerilog . — Očitko - Developed a game to improve eye muscle strength using LabVIEW. — Project in Robotics Engineering - process of making components using CNC machines and assembling them using DENSO robots.
SQL Jira C C++ Python Microsoft Windows Azure MATLAB LabVIEW svg Linux
— Design Verification Engineer focused on IP-level SV/UVM: built testbenches, scoreboards, constrained-random tests, and SystemVerilog Assertions (SVA). — Integrated the DUT with RAL and drove functional/code coverage closure. — Motivated to expand into subsystem and SoC-level verification, passionate about verification, and dedicated to continuous learning and growth. PROJECTS — Asynchronous FIFO – Design & Verification using SystemVerilog . — Očitko - Developed a game to improve eye muscle strength using LabVIEW. — Project in Robotics Engineering - process of making components using CNC machines and assembling them using DENSO robots.
SQL Jira C C++ Python Microsoft Windows Azure MATLAB LabVIEW svg Linux

Skills

Python
C++
C
SV/UVM
Jira
Matlab
SQL
LabVIEW
MS Office
Libre Office
Linux
Microsoft Windows,
Team Player
Communication
Creative
Persistent
Attention to Detail
Curious

Work experience

DESIGN VERIFICATION ENGINEER
08.2023 - 05.2025 |CAPGEMINI
SV/UVM, C, C++, Jira, Python, LabVIEW, SQL, Matlab, MS Office, Libre Office
● Worked on IP-level digital design verification using SystemVerilog/UVM. ●Developed a UVM testbench with multiple UVCs; modeled transactions, implemented a scoreboard, and used a virtual sequencer to coordinate sequences. ● Integrated the DUT with a RAL in the testbench and authored directed and constrained-random tests. ● Wrote SystemVerilog Assertions (SVA) and performed functional and code coverage analysis to close gaps. ● Performed waveform-based debug and simulation analysis, accelerating regression triage and failure reproduction. ● Collaborated via Git/SVN and automated flows with Bash scripting. ● Protocols: APB (hands-on); familiar with AXI, AHB, and UART.
INTERN
05.2022 - 06.2022 |NOFFZ FORSTEH TECHNOLOGIES
SV/UVM, C, C++, Jira, Python, LabVIEW, SQL, Matlab, MS Office, Libre Office
● Developed a Tetris game in LabVIEW.

Educational background

Electronics and Digital Systems (Masters Degree)
since 2025 - Till the present day
SCHOOL OF ELECTRICAL ENGINEERING, UNIVERSITY OF BELGRADE
Signals and Systems (Bachelor’s Degree)
2017 - 2022
SCHOOL OF ELECTRICAL ENGINEERING, UNIVERSITY OF BELGRADE

Languages

SerbianNativeEnglishProficient