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Registration: 29.07.2025

Mohamed Abdelrahman

Specialization: Digital Verification Engineer
— Bachelor’s degree holder in Electronics and Communications Engineering from Cairo University (Class of 2024), with a solid foundation in Digital IC Design, Verification, programming, and scripting. — A highly motivated Digital Verification Engineer with hands-on experience in Verilog, SystemVerilog, UVM, C++, and TCL. My graduation project focused on verifying the CXL 2.0 protocol using SystemVerilog and UVM. I have also worked on multiple verification projects, including: — Ethernet Protocol Verification using SystemVerilog and UVM. — UART Verification using SystemVerilog with DPI-C integration. — Aligner Verification using SystemVerilog and UVM. — These projects provided practical experience with advanced verification concepts such as UVM methodology, SystemVerilog Assertions (SVA), functional coverage, DPI, and Register Abstraction Layer (RAL) modeling using Questasim.
C C++ MATLAB Cadence OrCad
— Bachelor’s degree holder in Electronics and Communications Engineering from Cairo University (Class of 2024), with a solid foundation in Digital IC Design, Verification, programming, and scripting. — A highly motivated Digital Verification Engineer with hands-on experience in Verilog, SystemVerilog, UVM, C++, and TCL. My graduation project focused on verifying the CXL 2.0 protocol using SystemVerilog and UVM. I have also worked on multiple verification projects, including: — Ethernet Protocol Verification using SystemVerilog and UVM. — UART Verification using SystemVerilog with DPI-C integration. — Aligner Verification using SystemVerilog and UVM. — These projects provided practical experience with advanced verification concepts such as UVM methodology, SystemVerilog Assertions (SVA), functional coverage, DPI, and Register Abstraction Layer (RAL) modeling using Questasim.
C C++ MATLAB Cadence OrCad

Portfolio

Digital Design Verification of Ethernet MAC layer using SV-UVM

I am currently working on the functional verification of a 10 Gigabit Ethernet MAC (Media Access Control) layer, implementing and debugging testbenches using SystemVerilog UVM. This includes handling XGMII interfaces, verifying pause frame behavior, and integrating CRC-32 generation within UVM sequences.

Digital Design Verification of UART using SV-UVM depending on the SV-DPI to test the golden model

Developed a UVM-based testbench to verify UART functionality. Implemented sequence items, sequences, driver, monitor, scoreboard, and coverage model. Used DPI-C for C model integration and assertions for protocol checks. Simulated and debugged using Questasim.

Digital Design Verification of CXL (2.0) Data link layer using SV-UVM

My Role - Extracting the requirements of the Packer, Unpacker, and Credit Management Controller components. - Developing a comprehensive verification plan outlining the features to be tested using SVA and Scoreboard. - Building End-To-End Scoreboard to check the basic operation of the CXL. - Integrating the UVM environment with other teams using Virtual Sequencer and Virtual Sequence. Final target: - Reached 100% code and functional coverage for the verified blocks.

Skills

C
C++
MATLAB
Cadence OrCad
UVM
System Verilog
SVA
Constrained Random Verification
Functional Verification

Work experience

Digital Verification Intern
07.2023 - 07.2024 |Si-Vision
C, C++, MATLAB, SVA
● Extracting the requirements of the Packer, Unpacker, and Credit Management Controller components. ● Developing a comprehensive verification plan outlining the features to be tested using SVA and Scoreboard. ● Building End-To-End Scoreboard to check the basic operation of the CXL. ● Integrating the UVM environment with other teams using Virtual Sequencer and Virtual Sequence.

Educational background

Electronics and Electrical Communication (Bachelor’s Degree)
2019 - 2024
Cairo University Faculty of Engineering

Languages

EnglishAdvancedArabicNative