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Registration: 29.07.2025

Farhan Ali Shah

Specialization: Design Engineer
— Experienced Design Engineer with a strong background in RTL development, verification, and embedded systems. — Proficient in SystemVerilog and UVM, with hands-on experience in RISC-V architecture, test plan development, UVM testbench development, code coverage analysis, and RTL module design and implementation.
— Experienced Design Engineer with a strong background in RTL development, verification, and embedded systems. — Proficient in SystemVerilog and UVM, with hands-on experience in RISC-V architecture, test plan development, UVM testbench development, code coverage analysis, and RTL module design and implementation.

Portfolio

MRUT Cache replacement Policy

● Design and implimented MRUT cache replacement policy in CVA6.

Functional Verification of IOPMP IP

UVM-Based Functional Verification of IOPMP IP. ● Developed a UVM-based verification environment for the IOPMP IP. ● Authored 90+ functional tests and created a detailed test plan for comprehensive functional verification. ● Achieved 100% block and expression coverage for the full model of the IOPMP IP using Xcelium, ensuring complete functional validation and coverage closure.

Adding support for ZCMT Extension for Code-Size Reduction in CVA6

● This PR implements the ZCMT extension in the CVA6 core, targeting the 32-bit embedded-class platforms. ZCMT is a code-size reduction feature that utilizes compressed table jump instructions (cm.jt and cm.jalt) to reduce code size for embedded systems.

Skills

Verilog
System verilog
UVM
Functional Verification
Testbench development
Computer archetecture
Ip verfication
AXI
I2c
Digital system design
AHB protocols
UART
SPI
Python
C/C++
RISC-V Assembly
MATLAB
GitHub
GitLab
Bash
Make
Docker
Vivado
KiCad
SolidWorks
SketchUp
Inkscape
Draw.io
Latex

Work experience

Design Engineer
03.2024 - 05.2025 |10x Engineers
Digital Design, Verification, UVM, ZCMT, RISC-V
● UVM-Based Functional Verification of IOPMP IP: - Developed a UVM-based verification environment for the IOPMP IP. - Authored 90+ functional tests and created a detailed test plan for comprehensive functional verification. - Achieved 100% block and expression coverage for the full model of the IOPMP IP using Xcelium, ensuring complete functional validation and coverage closure. ● Lead the RTL design and implementation of the ZCMT extension in the CVA6 core: - Designed and implemented the ZCMT extension for code-size reduction in the open-source CVA6 core. - Developed a macro decoder module for ZCMT instructions, enabling efficient implicit memory access and enhancing system performance. - Achieved 100% functionality reliability through comprehensive validation and RISC-V assembly tests. ● Contributed in Global clinic Project of Harvey Mudd College: - Authored comprehensive test plans for both privileged and unprivileged architecture layers of RISC-V, aligning with the RVA22S64 profile specifications. - Contributed to the development of cvw-arch-verif, an open-source functional verification suite for RISC-V cores, in collaboration with Harvey Mudd College, UET Lahore, and 10xEngineers. ● Collaborated with cross-functional teams to streamline workflows and improve project timelines.
Associate Engineer
08.2023 - 03.2024 |10x Engineers
Digital Design, CVA6, System Verilog
● Implementation of MRUT Cache Replacement Policy in CVA6 Core: - Developed and implemented the MRUT Cache Replacement Policy in CVA6, optimizing cache performance. - Conducted directed tests to validate the design and ensure robust integration. ● Completed advanced training courses in System Verilog for Design, System Verilog for Verification, Digital Logic Design, and Computer Architecture.
Research Assistant
04.2019 - 08.2023 |Fablab, Sukkur IBA University
Research, Embedded systems, LoRa, OpenCV, Arduino, ESP32, Raspberry Pi, IoT
● Led diverse industrial and research-based hardware development projects: - Industrial SOS System using LoRa: Designed and fabricated a long-range wireless emergency alert system for industry to enhance on-site worker safety. - Robotic Manipulator: Developed a robotic arm integrated with a vision system using OpenCV to detect and sort objects. - Open-source 3D Printer: Designed and developed a customizable, cost-efficient printer for academic use. - Banana Fiber Extractor Machine: Engineered a mechanized solution for sustainable fiber extraction. ● Delivered hand-on teaching and Lab support in Embedded systems and Workshop practice courses, training the students in circuit designing, micro controller programming, 3D designing, IoT and FPGA development. ● Led and conduct 30+ technical workshops on Arduino, ESP32, Raspberry Pi, IoT, and drone programming, trained over 1,000 participants. ● Secured research grants through successful proposal writing, enabling the lab to expand its R&D capabilities. ● Mentored students in embedded systems labs, providing hands-on training in hardware integration and programming. ● Managed lab operations, overseeing procurement and resource allocation to ensure efficient functionality and a productive learning environment.

Educational background

Electronics and Communication (Masters Degree)
2017 - 2021
Sukkur IBA University
Electrical Engineering (Bachelor’s Degree)
2013 - 2017
Sukkur IBA University

Languages

EnglishProficientUrduNativeHindiAdvanced