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Registration: 02.08.2025

Pooja Satpute

Specialization: Design / Verification Engineer
Windows Verilog Debugging SAP Object Oriented Programming Python Branch Design Verification LabVIEW TcL Linux
Windows Verilog Debugging SAP Object Oriented Programming Python Branch Design Verification LabVIEW TcL Linux

Skills

Design Verification
Verilog
SystemVerilog
Python
TCL
LabVIEW
Windows
Linux
Object Oriented Programming
Debugging
Branch prediction
SAP
Siemens-QuestaSim
ModelSim
Synopsys VC Formal
EDA Playground
APB
I2C
MESI
MESIF
MOESI
Digital Logic Design
RTL Design
FSM Based Design
Formal Verification
Coverage Driven Verification
UVM
Assertion Based Verification
Architectures
Cache Coherence
Pipelining

Work experience

Advanced VLSI Design / Verification Engineer
09.2023 - 12.2023 |LucidVLSI
Verilog, SystemVerilog, UVM
● Received comprehensive Verilog, SystemVerilog, and UVM methodologies training. ● Developed proficiency in implementing class-based verification environments, utilizing stimulus generation techniques to debug and verify RTL logic effectively.
SAP Basis Consultant
06.2021 - 06.2023 |Atos Global IT Solutions & Services
SAP
● Managed SAP system monitoring, upgrades, license installations, and ticket resolution to ensure optimal performance and SLA complian.

Educational background

Electrical / Computer Engineering (Masters Degree)
2023 - 2025
Portland State University
Electronics / Telecommunication Engineering (Bachelor’s Degree)
2016 - 2020
Savitribai Phule Pune University

Languages

EnglishProficient