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Registration: 04.08.2025

Gurjot Singh

Specialization: ASIC Design Engineer
— I am specializing in digital and custom ASIC design. — My experience includes: Tapeout and Sign-off of custom neuromorphic chips (65nm and 180nm nodes), Designing testbenches and contributing to Physical Design flows, Hands-on experience with FPGA development, Working on RISC-V ISA and processor design. — These experiences have given me a strong foundation in digital design, verification, and backend flows.
Verilog MATLAB RTL FPGA TcL C++ Altium Python
— I am specializing in digital and custom ASIC design. — My experience includes: Tapeout and Sign-off of custom neuromorphic chips (65nm and 180nm nodes), Designing testbenches and contributing to Physical Design flows, Hands-on experience with FPGA development, Working on RISC-V ISA and processor design. — These experiences have given me a strong foundation in digital design, verification, and backend flows.
Verilog MATLAB RTL FPGA TcL C++ Altium Python

Skills

Verilog
SystemVerilog
Python
TCL
Verilog–A
C++
Cadence Virtuoso
Xcelium
Genus
Innovus
Xilinx Vivado
Open-Source EDA
Altium
LTspice
Matlab

Work experience

ASIC Design Intern
01.2024 - 07.2024 |Indian Space & Research Organisation (ISRO)
Verilog, Matlab, Verilog-A, C++
● Designed and completed layout of low PN VCO for a multi-GHz PLL for NavIC tranciever in 65nm RFCMOS. ● Developed models in Verilog-A for faster system level simulations of integer-N PLLs in Cadence Virtuoso. ● Delivered program for optimum bandwidth of a PLL based on VCO & XO phase noise measurements. ● Implemented a script to design loop filter from system specifications for 2nd and 3rd order with gamma param. ● Achieved the target phase noise of -100dBc/Hz at 100kHz with sub-500fs RMS Jitter after extraction.

Educational background

M.Tech in ESE/VLSI (Masters Degree)
since 2024 - Till the present day
Indian Institute of Science
Electrical and Electronics (Bachelor’s Degree)
2020 - 2024
Panjab University

Languages

EnglishAdvanced